1. Field of the Invention
The present invention relates to a semiconductor memory device, which is electrically rewritable, for example, including a nonvolatile semiconductor memory having memory cell arrays of NAND cell structure.
2. Description of the Related Art
As one of semiconductor memory devices, a NAND cell type EEPROM capable of integrating to a high degree is known. Structurally, plural memory cells are connected in series by sharing their source and drain between adjacent ones, and they are connected to a bit line as one unit. The memory cell usually has an FETMOS structure laminating a charge storage layer and a control gate. Memory cell arrays are integrated and formed in a p-type substrate or in a p-type well formed in n-type substrate. The drain side of the NAND cell is connected to the bit line through a selective gate, while the source side is connected to the source line (reference potential wiring) through the selective gate. The control gates of the memory cells are connected continuously in a line direction to form a word line.
The operation of NAND cell type EEPROM is as follows.
Data program operation starts sequentially from the memory cell at the remotest position from the bit line. A high potential Vpp (about 20 V) is applied to the control gate of the selected memory cell, an intermediate potential VM (about 10 V) is applied to the control gates and selective gates of the memory cells at the further bit line side, and either 0 V or intermediate potential is applied to the bit line corresponding to the data. When 0 V is applied to the bit line, its potential is transmitted up to the drain of the selected memory cell, and an electron injection occurs from the drain to the floating gate. As a result, the threshold voltage of the selected memory cell is shifted to the positive direction. This state is defined, for example, as data "1". When an intermediate potential is applied to the bit line, electron injection does not occur, and hence the threshold voltage is not changed and remains negative. This state is data "0".
Data erase operation is executed simultaneously on all cells in the NAND cell. That is, all control gates and selective gates are at 0 V, and the bit lines and source lines are in floating state, and in this condition a high potential of 20 V is applied to the p-type wells and n-type substrates. Consequently, electrons of floating gate are released to the p-type well in all memory cells, and the threshold voltage is shifted to the negative.
Data read operation is effected by setting the control gate of the selected memory cell at 0 V and the control gate and selective gates of all other memory cells at source potential VCC, and detecting whether an electric current flows or not in the selected memory cell.
As clear from the description of operation herein, in the NAND cell type EEPROM, in program and read operation, the nonselective memory cells act as transfer gates. From this viewpoint, the threshold voltage of a written memory cell has its own limit. For example, a preferred range of threshold voltage for the memory cell in which "1" is written is about 0.3 to 3.5 V. Considering changes after data program, fluctuations of manufacturing parameters of memory cells, and variations of source potential, the threshold voltage distribution after data programming is demanded to be a smaller range.
In the conventional method of programming data in same conditions in all memory cells by fixing the program potential and program time, however, it is difficult to keep the threshold voltage range after programming "1" within an allowable range. For example, memory cells may vary in characteristics due to fluctuations in manufacturing process. Therefore, reviewing program characteristics, there are easy-to-program memory cells and hard-to-program memory cells. By contrast, a method is proposed to program while verifying by adjusting the program time, so that the threshold voltage of each memory cell may settle within a desired range (Japanese Laid-open Patent No. 5-144277).
The threshold voltage of an erased memory cell must be a negative value. To realize this state securely, a method is known to erase while verifying by adjusting the erase time. Examples of operation timing of such program verify read and erase verify read are shown in FIGS. 1 and 2.
In both timing charts of FIGS. 1 and 2, a circuit shown in FIG. 3 is used as a sense amplifier/data latch circuit and latch data detecting circuit. The circuit in FIG. 3 includes a circuit (enclosed by broken line A) capable of detecting whether program or erase state is sufficient or not, without having to issuing the data of memory cells to outside, after confirming the program or erase state (Japanese Laid-open Patent No. 6-76586).
Points of notice in operation timing charts in FIGS. 1 and 2 are the star-marked section in FIG. 1 and asterisked section in FIG. 2. The operation timing in FIG. 1 is explained in the first place.
After charging all bit lines with VCC, by setting the word lines (control gates) and selective gates to "H", the bit lines connected to the memory cells having "1" data are kept at VCC, while the bit lines connected to the memory cells having "0" data are changed from VCC to 0 V. In succession, the bit lines connected to the memory cell having program data "1" are charged from 0 V to VH (voltage to be judged to be "H" level), and the bit lines are sensed. Sequentially, the signal RST changes from VCC to 0 V, node N0 floats, remaining at potential of 0 V, and APCON is changed from 0 V to VCC. At this time, if node N2 is at "L" level, that is, 0 V, node N0 is kept at 0 V, and hence Qn46 remains OFF.
When node N2 is at "H" level, for example, VCC, node N0 is changed up to (VCC-Vthn). If (VCC-Vthn) &lt;Vthn, Qn46 is turned on, and therefore VDTC in floating state is changed from VCC to 0 V. In this case, when nodes N1 of all data latch circuits are at "H" level and N2 at "L" level, VDTC is kept at VCC. This state corresponds to the program completion state of all selected memory cells, and hence programming is over.
In at least one of all data latch circuits, if node N1 is "L" and N2 is "H", VDTC changes from VCC to 0 V. It shows that programming is insufficient in at least one selected memory cell, and hence programming continues. This is a normal state.
However, if VCC-Vthn&lt;Vthn, Qn46 is always in OFF state, and data in all data latch circuits cannot be detected simultaneously, and the risk of an error is high. The state of VCC-Vthn&lt;Vthn is more likely to occur when the VCC is lower, and it is hard to reduce the source potential in the circuit shown in FIG. 3.
The same holds true in the asterisked section in FIG. 2.
As a method to solve this problem, a method is known to set SIGNALS APCON and AEON at higher voltage than VCC between star-mark and asterisk, but the operation is complicated in this method, and it takes a longer time to generate a voltage higher than VCC, which leads to various problems such as longer operation time and increase in the number of circuits.
As the circuit for program and erase verify read, instead of the circuit in FIG. 3, the circuit in FIG. 4 may be also used. In FIG. 4, there are a node for simultaneous detection VDTCP in program verify read, and a node for simultaneous detection VDTCE in erase verify read, and each is connected with the drain of n-channel transistor Qn47 for receiving nodes N2, N1 at the gate. By using this circuit, VCC is directly entered into the gates of the detecting transistors Qn47, Qn48 as "H" level, and if the VCC is reduced, error does not occur as far as VCC &gt;Vth.
In the circuit in FIG. 4, however, one wire is added (wiring for simultaneous detection is increased from VDTC only to VDTCP and VDTCE), and therefore the pattern area is increased.
On the other hand, in the conventional NAND cell type EEPROM, one sense amplifier/data latch circuit shown in FIG. 3 must be provided for each bit line, and the pattern area of the sense amplifier/data latch circuit increases because the sense amplifier/data latch circuit contains lots of elements. Therefore, as shown in FIG. 5A, a width for about four bit lines is needed on the pattern for one area of the sense amplifier/data latch circuit (S/Ai in FIG. 5A, where in=1, 2, . . . ) to form a pattern diagram of one sense amplifier/data latch circuit+one latch data detecting circuit (A in FIG. 3, corresponding to A of FIG. 4), and therefore the pattern diagram of the sense amplifier/data latch circuit may be stacked up in four layers. And a column decoder is provided beneath it (see FIG. 5A).
In the case of using the circuit structure of FIG. 3, the node of program/erase completion detecting signal is as shown in FIG. 5B. As known from FIG. 5B, since the program/erase completion detected signal node is extended into the pattern of the sense amplifier/data latch circuit, the wiring length of the program/erase completion detected signal node is very long. As a result, the capacity of the program/erase completion detected signal node becomes larger. In the methods shown in FIG. 5A and 5B, the program/erase completion detecting operation is the operation of checking if the VDTC node is discharged or not through the transistor Qn46 after once charging the program/erase completion detected signal node (equivalent to VDTC in FIGS. 5A and 5B) to VCC potential, and when the capacity of the VDTC node is large, the required time for charging and discharging of potential is longer, and a longer time is needed for program/erase completion detecting operation, and finally it takes a long time in program/erase verify read operation.
Of the charging and discharging operation, the charging operation of the VDTC node can be increased in speed by increasing the size of the transistor Qp6 in FIG. 5A, and since only one transistor Qp6 is used in the entire chip, if the size of Qp6 is increased, there is almost no area increase in the entire chip, so that high speed charging operation of the VDTC node may be easily realized. However, as for discharging operation of VDTC node, in order to realize high speed, there is no other way than to increase the size of the transistor Qn46, but since the number of transistors Qn46 is the same as the number of bit lines (usually thousands to tens of thousands, if the size is increased, the pattern area increases significantly, leading to a notable increase in the chip area. Still worse, if there is only one memory cell incomplete in program or erase, the result of program/erase completion detecting result is incomplete, and in a worst case, the VDTC node must be discharged through one transistor Qn46 in the required time of VDTC node discharge.
Therefore, when the VDTC node capacity is large, a longer time is needed for the VDTC n ode discharge in order to complete the discharge into "L" level within the VDTC node discharge time so as to keep reliability of the program/erase completion detecting operation, which leads to a problem of extension of the time of program/erase completion detecting operation, that is, extension of operation time of program/erase verify read, and when the dimension of the transistor for discharge is increased in order to shorten the VDTC node discharge time, the chip area is significantly increased.
Thus, in the conventional semiconductor memory device such as NAND cell type EEPROM, when the source potential is lowered, a longer time is required for program/erase verify read, and the risk of error is heightened.
Moreover, when detecting if program or erase is sufficient, that is, whether to complete program or erase or not, in all memory cells selected during program or erase verify read operation, the wiring length of the node to be detected (=node for simultaneous detection, corresponding to VDTC node in FIGS. 5A and 5B), is long, and therefore the capacity of the node to be detected becomes larger, and the required time for charging or discharging of the node to be detected is extended, and a longer time is required for program or erase verify read operation. Furthermore, to shorten the required time for charging or discharging of the node to be detected, when the dimension of the transistor responsible for charging or discharging is increased, since the number of transistors is about thousands or tens of thousand, the chip area is increased significantly.